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king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 1 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. - table of contents - 1. general des cription ___________________________________________________________________1 2. features _____________________________________________________________________________2 3. pin descri ption _______________________________________________________________________3 4. pad location _________________________________________________________________________5 5. lcd power supply____________________________________________________________________6 6. lcdc control register_________________________________________________________________7 7. lcd ram map_______________________________________________________________________8 8. oscillato rs ___________________________________________________________________________8 9. general purpo se i/o___________________________________________________________________9 10. timer1 ___________________________________________________________________________11 11. timer2 ___________________________________________________________________________12 12. watch dog timer __________________________________________________________________14 13. pulse-width mo dulation ____________________________________________________________14 14. summary of registers and mask options ______________________________________________15 15. absolute maxi mum rating __________________________________________________________17 16. recommended operati ng conditions _________________________________________________17 17. ac/dc charact eristics _____________________________________________________________17 18. application circuit_________________________________________________________________18 1. general description HE83R123 is a member of 8-bit mcu series devel oped by king billion. 32 lcd segment driver pins are multiplexed with i/o pins to provide flexibility of wi de variety of combinations to suit the needs of applications users can choose any one of combinations from 320 dots lcd driver with 8 bit i/o port to 64 dots lcd driver with 40-bit i/o port, etc. by mask option. the built-in lcd power regulator can provide stable lcd display effect over wide range of battery voltage . the pulse width modulation with complementary outputs provides the complete speech output mechanism. the 64k rom can store around 20 second of speech. this chip is applicable to the small/medium systems such as lcd games, perpetual calendar etc. the instruction set or he80000 easy to l earn and use. most of instructions take only 3
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 2 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. oscillator clocks. this chip is suitable for the applications that require higher performance. 2. features 9 operation voltage: 2.4v ~ 5.5v 9 system clock: dc ~ 8 mhz @ 5.0v dc ~ 4 mhz @ 2.4v 9 internal rom: 64 kb 9 internal ram: 256 bytes 9 dual clock system: fast clock: 32768 ~ 8m hz slow clock: 32768 hz 9 4 operation modes: fast, slow, idle, sleep modes. 9 watch dog timer to prevent deadlock condition. 9 40-bit bi-directional i/o port with push-pull or op en-drain output type selectable for each i/o pin by mask option. 32 of them are multiplexed with lcd segment pins. 9 64 (8 com x 8 seg) ~ 320 (8 com x 40 seg) dot lcd driver. 9 built-in lcd power regulator to provid e stable working voltage (~3volt) ? when vdd R 2.4volt, lv4 output voltage around 3volts. ? when vdd 2.4volt lv4, 3, 2, 1 output voltage will going down with vdd 9 complementary pulse-width modulation outputs. 9 two external interrupts and two internal timer interrupts. 9 two 16-bit timers. 9 instruction set: 32 instructions with 4 addressing modes. 9 application field: lcd games, perpetual calendar, etc.
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 3 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. 3. pin description HE83R123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 vdd pwmp pwmn gnd prt177 prt176 prt175 prt174 prt173 prt172 prt171 prt170 prt157 prt156 prt155 prt154 prt153 prt152 prt151 prt150 prt147 prt146 prt145 prt144 prt143 prt142 prt141 prt140 prt117 prt116 prt115 prt114 prt113 prt112 prt111 prt110 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 com5 com4 com3 com2 com1 com0 lc1 lc2 lvf lv1 lv2 lv3 lv4 gnd rstp fxo fxi tstp sxo sxi vdd prtd7 prtd6 prtd5 prtd4 prtd3 prtd2 prtd1 prtd0 pin name pin # i/o description vdd 1 p dedicated power for pulse width modulation output. pwmp 2 o pulse width modulation output. pwmn 3 o complementary output to pwmp. gnd 4 p dedicated power for pulse width modulation output. prt17[7..0] 5 ~ 12 b/ o 8-bit bi-directional i/o port 17 is shared with lcd segment pads seg[39..32]. the function of the pad can be selected individually by mask options mo_lio17[7..0]. (?1? for lcd and ?0? for i/o). the output type of i/o pad can also be selected by mask option mo_17pp[7..0] (1 for push-pull and ?0? for open-drain). as the output structure of i/o pad does not contain tri-state b uffer. when using the i/o as input, ?1? must be outputted before reading. prt15[7..0] 13 ~ 20 b/ o 8-bit bi-directional i/o port 15 is shared with lcd segment pads seg[31..24]. the function of the pad can be selected individually by mask options mo_lio15[7..0]. (?1? for lcd and ?0? for i/o). the output type of i/o pad can also be selected by mask option mo_15pp[7..0] (1 for push-pull and ?0? for open-drain). as the output structure of i/o pad does not contain tri-state b uffer. when using the i/o as input, ?1? must be outputted before reading. prt14[7..0] 21 ~ 28 b/ o 8-bit bi-directional i/o port 14 is shared with lcd segment pads seg[23..16]. the function of the pad can be selected individually by mask options mo_lio14[7..0]. (?1? for lcd and ?0? for i/o). the output type of i/o pad can also be selected by mask option mo_14pp[7..0] (1 for push-pull and ?0? for open-drain). as the output structure of i/o pad does not contain tri-state b uffer. when using
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 4 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. pin name pin # i/o description the i/o as input, ?1? must be outputted before reading. prt11[7..0] 29 ~ 36 b/ o 8-bit bi-directional i/o port 11 is shared with lcd segment pads seg[15..8]. the function of the pad can be selected individually by mask options mo_lio11[7..0]. (?1? for lcd and ?0? for i/o). the output type of i/o pad can also be selected by mask option mo_11pp[7..0] (1 for push-pull and ?0? for open-drain). as the output structure of i/o pad does not contain tri-state b uffer. when using the i/o as input, ?1? must be outputted before reading. seg[7..0] 37 ~ 44 o lcd segment seg[7..0] outputs. com[7..0] 45 ~ 52 o lcd common driver pads. lc1 53 b charge pump capacitor pin lc2 54 b charge pump capacitor pin lvf 55 i regulator feedback input. the regulator output voltage can be adjusted by the resistor between lv1 and lvf pads lv1 56 b lcd charge pump voltage v1 lv2 57 b lcd charge pump voltage v2 lv3 58 b lcd charge pump voltage v3 lv4 59 b lcd charge pump voltage v4 gnd 60 p power ground input. rstp_n 61 i system reset input pin. level trigger, active low on this pin will put the chip in reset state. fxo, fxi 62, 63 o, b external fast clock pin. two types of oscillator can be selected by mo_fxtal (?0? for rc type and ?1? for crystal type). for rc type oscillator, one resistor need to be connected between fxi and gnd. for crystal oscillator, one crystal need to be placed between fxi and fxo. please refer to application for details. tstp_p 64 i test input pin. please bond this pad and reserve a test point on pcb for debugging. but for improving esd, please connect this point with zero ohm resistor to gnd . sxo, sxi 65, 66 o, i external slow clock pins. slow clock is clock source for lcd display, timer1, time-base and other internal blocks. both crystal and rc oscillator are provided. the slow clock type can be selected by mask option mo_sxtal. choose ?0? for rc type and ?1? for crystal oscillator. vdd 67 p positive power input. 0.1 f decoupling capacitors should be placed as close to ic vdd and gnd pads as possible for best decoupling effect. prtd[7..0] 68 ~ 75 b 8-bit bi-directional general purpose i/o por t d. the output type of i/o pad can also be selected by mask option mo_dpp[7..0] (?1? for push-pull and ?0? for open-drain). as the output structure of i/o pad does not contain tri-state b uffer. when using the i/o as input, ?1? must be outputted before reading the pin. prtd[7..2] can be used as wake-up pins . prtd[7..6] can be used as external interrupt sources.
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 5 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. 4. pad location die size: 2350 m * 3090 m substrate connect with gnd product name p r t d [ 0 ] p r t d [ 1 ] p r t d [ 2 ] p r t d [ 3 ] p r t d [ 4 ] p r t d [ 5 ] p r t d [ 6 ] p r t d [ 7 ] v d d s x i s x o t s t p | p f x t f x o r s t p | n g n d l v 4 l v 3 p r t 15 [2] p r t 15 [1] p r t 15 [0] p r t 14 [7] p r t 14 [6] p r t 14 [5] p r t 14 [4] p r t 14 [3] p r t 14 [2] p r t 14 [1] p r t 14 [0] p r t 11 [7] p r t 11 [6] p r t 11 [5] p r t 11 [4] p r t 11 [3] p r t 11 [2] p r t 11 [1] p r t 11 [0] lv2 lv1 lvf lc2 lc1 com[0] com[1] com[2] com[3] com[4] com[5] com[6] com[7] seg[0] seg[1] seg[2] seg[3] seg[4] seg[5] seg[6] seg[7] vdd pwmp pwmn gnd prt17[7] prt17[6] prt17[5] prt17[4] prt17[3] prt17[2] prt17[1] prt17[0] prt15[7] prt15[6] prt15[5] prt15[4] prt15[3]
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 6 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. pin number pin name x coordinate y coordinate pin number pin name x coordinate y coordinate 1 vdd -1110.00 1173.40 39 seg[5] 1110.00 -890.90 2 pwmp -1110.00 974.10 40 seg[4] 1110.00 -775.50 3 pwmn -1110.00 699.30 41 seg[3] 1110.00 -660.10 4 gnd -1110.00 500.10 42 seg[2] 1110.00 -544.70 5 prt17[7] -1110.00 263.10 43 seg[1] 1110.00 -429.30 6 prt17[6] -1110.00 147.70 44 seg[0] 1110.00 -313.90 7 prt17[5] -1110.00 32.30 45 com[7] 1110.00 -198.50 8 prt17[4] -1110.00 -83.10 46 com[6] 1110.00 -83.10 9 prt17[3] -1110.00 -198.50 47 com[5] 1110.00 32.30 10 prt17[2] -1110.00 -313.90 48 com[4] 1110.00 147.70 11 prt17[1] -1110.00 -429.30 49 com[3] 1110.00 263.10 12 prt17[0] -1110.00 -544.70 50 com[2] 1110.00 378.50 13 prt15[7] -1110.00 -660.10 51 com[1] 1110.00 493.90 14 prt15[6] -1110.00 -775.50 52 com[0] 1110.00 609.30 15 prt15[5] -1110.00 -890.90 53 lc1 1110.00 724.70 16 prt15[4] -1110.00 -1006.30 54 lc2 1110.00 840.10 17 prt15[3] -1110.00 -1121.70 55 lvf 1110.00 955.50 18 prt15[2] -1076.35 -1480.00 56 lv1 1110.00 1070.90 19 prt15[1] -960.95 -1480.00 57 lv2 1110.00 1186.30 20 prt15[0] -807.55 -1480.00 58 lv3 1018.00 1480.00 21 prt14[7] -692.15 -1480.00 59 lv4 902.60 1480.00 22 prt14[6] -576.75 -1480.00 60 gnd 787.20 1480.00 23 prt14[5] -461.35 -1480.00 61 rstp_n 671.80 1480.00 24 prt14[4] -345.95 -1480.00 62 fxo 556.40 1480.00 25 prt14[3] -230.55 -1480.00 63 fxi 441.00 1480.00 26 prt14[2] -115.15 -1480.00 64 tstp_p 325.60 1480.00 27 prt14[1] 0.25 -1480.00 65 sxo 166.20 1480.00 28 prt14[0] 115.65 -1480.00 66 sxi 5.05 1480.00 29 prt11[7] 231.05 -1480.00 67 vdd -110.35 1480.00 30 prt11[6] 346.45 -1480.00 68 prtd[7] -288.90 1480.00 31 prt11[5] 461.85 -1480.00 69 prtd[6] -404.30 1480.00 32 prt11[4] 577.25 -1480.00 70 prtd[5] -519.70 1480.00 33 prt11[3] 692.65 -1480.00 71 prtd[4] -635.10 1480.00 34 prt11[2] 808.05 -1480.00 72 prtd[3] -750.50 1480.00 35 prt11[1] 923.45 -1480.00 73 prtd[2] -865.90 1480.00 36 prt11[0] 1076.85 -1480.00 74 prtd[1] -981.30 1480.00 37 seg[7] 1110.00 -1121.70 75 prtd[0] -1096.70 1480.00 38 seg[6] 1110.00 -1006.30 5. lcd power supply the lcd power supply is equipped w ith input power regulator, voltage charge pumt, and bias voltage generating resistor network. the input power of mcu is regulated and multiplied by 4 times to generate lcd bias for lcd driver. the regulat or output voltage can be adjusted by the resi stor between lv1 and
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 7 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. lvf pads. lv4 lv3 lv2 lv1 lvf lc2 lc1 104 0.1uf r 0.1uf 0.1uf 0.1uf with the regulated lcd power, the lcd display can gi ve steady visual effect over a wide range of operating voltage. the built-in regulator must be enabled by mask option mo_ lvrg to function. mo_lvrg function 0 disable lcd regulator 1 enable lcd regulator please note that to emulate the visu al effect of 1/4 bias on the ice 3.x version the lr2 and lr3 on the top board need be shorted. 6. lcdc control register lcd control register lcdc contro ls the functions of lcd driver; such as contrast level, lcd waveform type, on/off, blank, etc. lcdc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - type blank lcde field value function type 0 select type a lcd waveform 1 select type b lcd waveform blank 0 normal display 1 lcd display blanked. lcd driver changes only com output signal, seg signal remains unchanged. lcde 0 lcd driver disabled, lc d driver has no output signal. 1 lcd driver enabled please note that lcd driver must be turned off before the entering sl eep mode. that means user must clear the bit 0 of lcdc to turn off lcd driving circ uit before setting bit 6 of op1 to enter sleep mode. large current might happen if the procedure is not followed. please also note that lcd driver uses slow clock as clock source. the lcd display will not display normally if it works in fast clock only mode because the lcd refresh action is too fast.
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 8 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. 7. lcd ram map seg[39..32] seg[31..24] seg[ 23..16] seg[15..8] seg[7..0] com0 f8h f0h e8h e0h d8h com1 f9h f1h e9h e1h d9h com2 fah f2h eah e2h dah com3 fbh f3h ebh e3h dbh com4 fch f4h ech e4h dch com5 fdh f5h edh e5h ddh com6 feh f6h eeh e6h deh com7 ffh f7h efh e7h dfh 8. oscillators the mcu is equipped with two clock sources with a variety of selections on the types of oscillators to choose from. so that system designer can select oscillator types based on the cost target, timing accuracy requirements etc. with two clock sources availabl e, the system can switch among operation modes of normal, slow, idle, and sleep modes by the setting of op1 and op2 registers as shown in tables below to suit the needs of application such as power saving, etc. op1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 field 1 stop slow inte t2e t1e z c mode r r/w r/w r/w r/w r/w r/w r/w reset 1 0 0 0 0 0 - - op2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 field idle pnwk tcwk - - - - - mode r/w r/w r/w - - - - - reset 0 - - 0 - - - - crystal, resonator or the rc oscillator or internal rc can be used as fast clock source. if the internal rc oscillator is used, then no external component is necessary. please note that oscillation frequency of internal rc oscillator may vary with parameters of ic fabrication pro cess. therefore if timing accuracy is essential in targeted applications, then internal rc is not recommended. name value function mo_fosce 0 internal fast osc 1 external fast osc mo_frci_s[2:0] 000 rfrc_i ~= 500k 001 rfrc_i ~= 1m 010 rfrc_i ~= 1.5m 011 rfrc_i ~= 2m 100 rfrc_i ~= 2.5m
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 9 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. 101 rfrc_i ~= 3m 110 rfrc_i ~= 3.5m 111 rfrc_i ~= 4m when crystal oscillator or external rc are used, co mponents should be placed as close to the pins as possible. the type of oscillator used is selected by mask option mo_fxtal. mo_fxtal fast clock type 0 rc oscillator. 1 crystal oscillator. vdd fxi fxi fxo c r two types of oscillator, crystal an d rc, can be used as slow clock by mask option mo_sxtal. if used in for time keeping function or other applications that required the accurate timing, crystal oscillator is recommended. if the timing accuracy is not important, then rc type oscill ator can be used to reduce cost. mo_sxtal slow clock type 0 rc oscillator 1 crystal oscillator sxi sxi sxo sxo crystal osc. rc osc. if the dual clock mode is used, the lcd display, timer1 and timer base will deri ve its clock source from slow clock while the other blocks will operate with the fast clock. 9. general purpose i/o there is one dedicated general purpose i/o port pr td. all the i/o ports are bi-directional and of non-tri-state output structure. th e output has weak sourcing (50 a) and stronger sinking (1 ma) capability and each can be configured as push-pull or open-drain output struct ure individually by mask
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 10 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. option. the input port has built-in sc hmidt trigger to prevent it from chattering. the hysteresis level of schmidt trigger is 1/3 vdd. mo_dpp[7..0] output structure 0 open-drain output 1 push-pull output when the i/o port is used as input, the weakly high sourcing pmos can be used as pull-up. open drain can be used if the pull-up is not required and let the external driver to drive the pin. please note that a floating pad could cause more power consumption since the noise coul d interfere with the circuit and cause the input to toggle. a ?1? needs to be written to port first before reading the input data from the i/o pin, otherwise, the pin will always be stuck at ?0?. if the pmos is used as pull-up, care should be taken to avoid the constant power drain by dc path between pull-up and external circuit. vdd vdd q q' latch mo_?pp sc h mi d t trigger input dout pad din prt11[7..0], prt14[7..0], prt15[7..0] and prt17[7..0] share pads with seg[8..39]. the function of the pins is selected by mask option mo_lio11, mo _lio14, mo_lio15, mo_lio17 respectively as shown in the following figure.
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 11 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. prt110 prt110 seg8 prt111 prt111 seg9 prt112 prt112 seg10 prt113 prt113 seg11 prt114 prt114 seg12 prt115 prt115 seg13 prt116 prt116 seg14 prt117 prt117 seg15 prt140 prt140 seg16 prt141 prt141 seg17 prt142 prt142 seg18 prt143 prt143 seg19 prt144 prt144 seg20 prt145 prt145 seg21 prt146 prt146 seg22 prt147 prt147 seg23 prt150 prt150 seg24 prt151 prt151 seg25 prt152 prt152 seg26 prt153 prt153 seg27 prt154 prt154 seg28 prt155 prt155 seg29 prt156 prt156 seg30 prt157 prt157 seg31 prt170 prt170 seg32 prt171 prt171 seg33 prt172 prt172 seg34 prt173 prt173 seg35 prt174 prt174 seg36 prt175 prt175 seg37 prt176 prt176 seg38 prt177 prt177 seg39 mo_lio11=0 mo_lio11=1 mo_lio14=0 mo_lio14=1 mo_lio15=0 mo_lio15=1 mo_lio17=0 mo_lio17=1 10. timer1 the timer1 consists of two 8-bit write-only preloa d registers t1h and t1l and 16-bit down counter. if timer1 is enabled, the counter will decrement by one with each incomi ng clock pulse. timer1 interrupt will be generated when the counter underflows - counts down to ffffh. and the counter will be automatically reloaded with the value of t1h and t1l. the clock source of timer1 is derived from slow cl ock ?sck? at dual clock or slow clock only mode. and it comes from the fast clock ?fck? at fast clock only mode. please note that the interrupt is generated when counter counts from 0000h to ffffh. if the value of t1h and t1l is n, and count down to ffffh, the to tal count is n+1. the cont ent of counter is zero when system resets. once it is enabled to count at this moment, interrupt will be generated immediately and value of t1h and t1l will be loaded since it counts to ffffh. so the t1h and t1l value should be set before enabling timer1.
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 12 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. t1h t1l "timer1 counter" decreases 1 count to 0xffffh auto reload when timer1 underflo w no start timer1 interrupt request. yes the contents of t1h and t1l almost loaded into timer1 immediately when timer1 is turned o n after reset. t1_int the timer1 related control registers are list as below: register address field bit position mode description ier 0x02 tc1_ier 2 r/w 0: tc1 interrupt is disabled. (default) 1: tc1 interrupt is enabled. t1l 0x03 t1l[7:0] 7~0 w low byte of tc1 pre-load value t1h 0x04 t1h[7:0] 7~0 w high byte of tc1 pre-load value op1 0x09 tc1e 2 r/w 0: tc1 is disabled. (default) 1: tc1 is enabled. 11. timer2 timer2 is similar in structure to timer1 except that clock source of timer2 comes from the system clock ?f sys ?/1.5. the system clock ?f sys ? varies depending on the operation modes of the mcu. the timer2 consists of two 8-bit write-only preloa d registers t2h and t2l and 16-bit down counter. if timer2 is enabled, counter will decrement by one w ith each incoming clock pulse. timer2 interrupt will
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 13 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. be generated when the counter underflows - counts dow n to ffffh. and it will be automatically reloaded with the value of t2h and t2l. please note that the interrupt signa l is generated when counter count s from 0000h to ffffh. if the value of counter is n, and count down to ffffh, the total c ount is n+1. the content of counter is zero when system resets. once it is enabled to count at this time, the interrupt will be generated immediately and value of t2h and t2l will be loaded since the counter counts to ffffh. so the t2h and t2l value should be set before enabling timer2. t2h t2l "timer2 counter" decreases 1 count to 0xffffh auto reload when timer2 underflo w no start timer2 interrupt request. yes the contents of t2h and t2l almost loaded into timer2 immediately when timer2 is turned o n after reset. t2_int the timer2 related control registers are list as below: register address field bit position mode description ier 0x02 tc2_ier 1 r/w 0: tc2 interrupt is disabled. (default) 1: tc2 interrupt is enabled. t2l 0x05 t2l[7:0] 7~0 w low byte of tc2 pre-load value t2h 0x06 t2h[7:0] 7~0 w high byte of tc2 pre-load value op1 0x09 tc2e 3 r/w 0: tc2 is disabled. (default)
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 14 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. register address field bit position mode description 1: tc2 is enabled. 12. watch dog timer watch dog timer (wdt) is designed to reset system automatically prevent system dead lock caused by abnormal hardware activities or program execution. wdt needs to be enabled in mask option. mo_wdte function 0 wdt disable 1 wdt enable to use wdt function, ?clrwdt? instruction needs to be executed in every possible program path when the program runs normally in order to clears the wdt counter befo re it overflows, so that the program can operate normally. when abnormal condi tions happen to cause the mcu to divert from normal path, the wdt counter will not be cleared and reset signal will be generated. wdt is the enabling signal generated by calculating 32768-clock overflow. rese t register content is same as tc1 (timer1 clock), which uses the same cl ock count source. wdt function can be generated in normal, slow and idle mode. however, wdt will not function during sleep mode (as the tc1 clock has stopped.) 13. pulse-width modulation the pulse-width modulator (pwm) converts 7-bit unsigne d speech data written to pw mc data register to proportional duty cycle of pwm output. pwm modul e shares the pwmc data register with digit-to-analog converter. so pwm and da output can exist at the same time. when pwm circuit is enabled, it generates signal with duty ratio in proportion to the da value. da = 0x20 da = 0x80 da = 0xe0 1 subframe the pwm bit of voc register controls register to enable the circuit a nd output driver. when pwm bit of
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 15 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. voc is ?0?, pwme bit and output drivers settings are both cleared. to use pwm for voice output, pwm bit has to be set to ?1? first, then set pwme bit and enable output driver by sett ing the driver number. if pwm bit is disabled and enabled again, the sett ing for driver and pwme bit will be clear. the fast clock is gated through pwme bit of pwmc command register to provi de the clock source of pwm circuit when it is enabled. as pwm needs highe r frequency to operate, it cannot generate correct pwm signal in slow clock only mode. when the program enters into sleep mode or idle m ode, it will automatically turn off all voice outputs by clearing voc[2..1] to ?00?. to ac tivate voice output again when retu rning to normal mode, the voc register needs to be set again. the pwm output volume can be adjusted by command register pwmc[6..4]. the bit 6 and 5 control 2 time driver, while bit 4 controls 1 ti me driver, thus it has 5 levels of driver output. by turning on/off the internal drivers, the sound level of pwm output can be turned up and down. please note that this adjustment apply only to pwm, but not da output. pwm output driver selection pwmc[6..4] number of driver 000 off 001 1 010 2 011 3 100 2 101 3 110 4 111 5 14. summary of registers and mask options all the registers and mask options used in this chip are listed in the following tables. address name field mode reset 00h tpl table pointer high byte w xxxx xxxx 01h tph table pointer low byte w xxxx xxxx 02h ier - - - - int1 t1 t2 int2 r/w --00 0000 03h t1l timer 1 low byte w xxxx xxxx 04h t1h timer 1 high byte w xxxx xxxx 05h t2l timer 2 low byte w xxxx xxxx 06h t2h timer 2 high byte w xxxx xxxx 07h sp stack pointer r/w 1111 1111 08h dp data ram pointer r/w xxxx xxxx 09h op9 drdy stop slow inte t2e t1e z c r/w 1000 00xx 0ah opa idle pnwk tcwk - - - - - r/w 0xx- ---- 0bh pp ram page pointer r/w 0000 0000 0dh prtd i/o port d r/w 1111 1111 oeh pwmc 1 pwm o/p driver - - - pwme w x000 xxxx oeh pwmc 0 7-bit da and pwm output data w xxxx xxxx 0fh lcdc - - - - - type blank lcde w xx1x xx10
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 16 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. address name field mode reset 11h prt11 i/o port 11 r/w 1111 1111 13h voc - - - - - pwm dac op w ---- -000 14h prt14 i/o port 14 r/w 0000 0011 15h prt15 i/o port 15 r/w 0000 0011 16h tpp rom table page pointer w 0000 0000 17h prt17 i/o port 17 r/w 1111 1111 mask options: name value note mo_pore 0 power-on reset disable 1 power-on reset enable mo_fosce 0 internal fast osc 1 external fast osc, use it now mo_fxtal 0 r/c oscilla tor for fast clock 1 crystal oscillator for fast clock mo_frci_s[2:0] 000 rfrc_i ~= 500k 001 rfrc_i ~= 1m 010 rfrc_i ~= 1.5m 011 rfrc_i ~= 2m 100 rfrc_i ~= 2.5m 101 rfrc_i ~= 3m 110 rfrc_i ~= 3.5m 111 rfrc_i ~= 4m mo_sxtal 0 r/c oscillator for 32k clock 1 crystal oscillator for 32k clock mo_fck/sckn 00 slow clock only 01 illegal 10 dual clock 11 fast clock only mo_wdte 0 wdt disable 1 wdt enable mo_cpp[7:0] 0 open-drain output 1 push-pull output mo_dpp[7:0] 0 open-drain output 1 push-pull output mo_11pp[7:0] 0 open-drain output 1 push-pull output mo_14pp[1:0] 0 open-drain output 1 push-pull output mo_15pp[1:0] 0 open-drain output 1 push-pull output mo_17pp[7:0] 0 open-drain output 1 push-pull output mo_lio11[1:0] 0 io pin 1 lcd pin mo_lio14[7:0] 0 io pin 1 lcd pin mo_lio15[1:0] 0 io pin 1 lcd pin mo_lio17[7:0] 0 io pin 1 lcd pin mo_lvrg 0 lcd regulator disable 1 lcd regulator enable
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 17 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. 15. absolute maximum rating item sym. rating condition supply voltage v dd -0.5v ~ 8v input voltage v in -0.5v ~ v dd +0.5v output voltage v o -0.5v ~ v dd +0.5v operating temperature t op 0 c ~ 70 c storage temperature t st -50 c ~ 100 c 16. recommended operating conditions item sym. rating condition supply voltage v dd 2.4v ~ 5.5v v ih 0.9 v dd ~ v dd input voltage v il 0.0v ~ 0.1 v dd 8mhz v dd =5.0v operating frequency f max 4mhz v dd =2.4v operating temperature t op 0 0 c ~ 70 0 c storage temperature t st -50 0 c ~ 100 0 c 17. ac/dc characteristics test condition: temp. = 25 , v dd = 3v 10%, gnd=0v parameter symbol min typ max unit condition normal mode current i fast 0.75 1 ma 2m ext. r/c slow mode current i slow 10 20 a 32768 hz, lcd disabled idle mode current i idle 6 10 a 32768 hz, lcd disabled additional current if lcd on i lcd 12 20 a lcd enabled, regulator on sleep mode current i sleep 1 a input high voltage v ih 0.8 v dd input pins input low voltage v il 0.2 v dd input pins input hysteresis width v hys 1/3 v dd i/o, rstp_n, threshold=2/3v dd (input from low to high) threshold=1/3v dd (input from high to low) output source current i oh 50 a output drive high*1, v oh =2.0v output sink current i ol1 1.0 ma output drive low, v ol = 0.4v input low current i il2 100 a i/o, v il = gnd, pull high internally input low current i il1 20 a rstp_n, v il = gnd, pull high internally 10 14 ma pwm *2 with 32 ? loading 6 8 ma with 64 ? loading pwm output current i pwm 4 5 ma with 100 ? loading note:
king billion electronics co., ltd E | ? HE83R123 he80000 series march 13, 2003 18 v1.0e this specification is subject to change without notice. pl ease contact sales person for th e latest version before use. 1. source current spec. applies to push-pull i/o port only 2. this spec. is based on one driver only. there are totally five dr ivers, so user must multiply the number of driver actually used to get the total amount of current. ( i pwm x n; n=0,1,2,3,4,5) 18. application circuit vdd vdd vdd vdd lv4 lv3 lv2 lv1 pwmp lvf lc2 pwmn lc1 com0 com1 com2 prt177 com3 prt176 com4 prt175 com5 prt174 com6 prt173 com7 prt172 seg0 prt171 seg1 prt170 seg2 prt157 seg3 prt156 seg4 prt155 seg5 prt154 seg6 prt153 seg7 prtd0 prt152 prtd1 prt151 prtd2 prt150 prtd3 prt147 prtd4 prt146 prtd5 prt145 prtd6 prt144 prtd7 prt143 prt142 sxi prt141 sxo prt140 prt117 fxi prt116 fxo prt115 reset prt114 prt113 lv4 prt112 lv3 prt111 prt110 0 r + 47uf 0.1uf 0.1uf 0.1uf 0.1uf 104 3.0v 1 2 0.47uf 0.1uf y2 32768hz 33p y6 4mhz 33p 22p 22p r HE83R123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 vdd pwmp pwmn gnd prt177 prt176 prt175 prt174 prt173 prt172 prt171 prt170 prt157 prt156 prt155 prt154 prt153 prt152 prt151 prt150 prt147 prt146 prt145 prt144 prt143 prt142 prt141 prt140 prt117 prt116 prt115 prt114 prt113 prt112 prt111 prt110 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 com5 com4 com3 com2 com1 com0 lc1 lc2 lvf lv1 lv2 lv3 lv4 gnd rstp fxo fxi tstp sxo sxi vdd prtd7 prtd6 prtd5 prtd4 prtd3 prtd2 prtd1 prtd0

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